In high density memory systems, a typical non-volatile memory cell may include a metal-oxide semiconductor (MOS) transistor having a parameter, e.g., a transistor device threshold voltage, that may be varied for storing a desired information, e.g., by injecting charges into a floating gate or gate oxide. Accordingly, a current sunk by the memory cell in determining biasing states varies depending on the information stored therein. For example, to store information in a twin-transistor memory cell there is provided two different threshold voltage values for the cell, with each different threshold voltage value associated with a different logic or bit value.
For example, FIG. 1A shows an exemplary non-volatile memory CMOS thin-oxide multi-time programmable memory (MTPM) array 10 which may be part of a memory device, or system. The array consists of plurality of memory cells 11 arranged by 2 dimensional matrix (e.g., m rows and n columns). For simplicity. FIG. 1 shows one column (e.g., n=1) having two rows (e.g., m=2) or two memory cells 11, however the actual memory consists of significantly more cells 11. More specifically, the MTPM array 10 consists of a plurality of twin-transistor memory cells 11 including first and second transistors 15A, 15B. They are connected with a common node 13, coupling to the source line (SL) running vertically and coupling with other cells in the same column in the array 10. In this example, SL is coupled to 0V or Grounded (GND). However, the SL can be coupled to another SL voltage. One terminal 14 of the first transistor 15B of a memory cell 11 and the terminal 16 of the second transistor 15A of the memory cell 11 are coupled to the bitline true (BLT) and the bitline complement (BLC) running vertically, respectively, and coupling to the cells in same column in the array 10.
The MTPM array 10 shown in FIG. 1A further includes two gate electrodes 20A, 20B respectively of the respective first and second transistors 15A, 15B and which are connected to a common wordline (WL) conductor 50, running horizontally, and coupling to other cells in a same row in the array 10.
Prior to use of the memory device 10, the cell 11 should be programmed by increasing one of the transistor threshold voltage (Vt) of the twin transistors 15A and 15B. More specifically, the transistor of the cell undergoes a Vt shift when it is programmed. Typical Vt values without Vt shift (or before programming) may range from about 0.25V to 0.3V. Typical Vt values with Vt shift (or after programming) may range from about 0.45V to 0.5V. In this example, the first transistor 15A is shown exhibiting a first threshold voltage (Vt), e.g., its native Vt or initial value, and the second transistor 15B programmed to exhibit an induced second threshold voltage, e.g., a Vt+shift (added) voltage. However, the VT states of the first and second transistor are interchangeable. When transistor 15B VT has an adder, the state of the programmed cell is 0, and 15A cell has an adder, the state of the programmed cell is 1.
For a program operation, an input digital data signal Din represents a programmable bit value to be written to the target memory cell 11. More specifically, when the target memory cell 11 is subjected to a high gate, or wordline (WL) voltage (e.g., ˜2 to 2.2V), and high drain voltage, or the voltage applied to either the BLC or BLT (e.g., ˜1.5V-1.8V), with SL grounded, for a few milliseconds (i.e., when it is programmed), its Vt of the transistor (i.e. 15B or 15A) of the target memory cell 11 gets shifted from its nominal value (0.25V˜0.3V) to a higher value (e.g., ˜0.45 to 0.5V) due to BTI (Bias temperature instability) and HCl (hot carrier injection) effects. Write circuit drivers 25 may be implemented to generate and apply programming voltages for bitline true (BLT) and bitline complement (BLC) conductors for writing a bit voltage value to the cells 15A, 15B depending on the write bit 0 or 1. The target cell is accessed, e.g., via a voltage provided on the wordline WL 50 corresponding to a row of the memory cell, and bit cell voltage values are written to the T or C cell by applying appropriate voltages to the BLT and BLC terminals corresponding to a selected column (complementary lines) of the target memory cell 10. For example the target multi-time programmable bit cell programming voltages generated are applied to WL, BLT and BLC, e.g., while grounding the SL source line.
When no WL signal is applied, or the voltage applied to BL is 0V, the MOS transistors 15A, 15B do not conduct, resulting in retaining their programmed states. Combinations of voltages can be applied to the first terminal, second terminal and gate terminals of the memory cell 10 to program, inhibit program, read and erase the logic state stored by the MOS transistors.
FIG. 1B shows a chart 40 explaining different modes of operation of the multi-time programmable memory array 10 of FIG. 1A including example voltages at the terminals of the cell transistors 15A, 15B that provide cell states including stand-by, write, read and reset. In particular, these states are: 1) a standby state when respective BLT and BLC terminals 14, 16 are floating (or may be 0 Volts) with a wordline WL of 0.0 Volts applied to the gates of each transistor in the twin-cell 15B, 15A; 2) a write logic “0” state, e.g., when the respective BLT terminal 14 is at 1.7 Volts and BLC terminal 16 is floating (or may be at 0.0 Volts) with a wordline WL of 2.2 Volts applied to the gates of each transistor 15B, 15A; however, the voltages on BLT and BLC could be swapped to store a logic “1” value in the cell; 3) a read state, e.g., when a wordline WL of 1.0 Volt (VDD) is applied to the gates of each transistor 15B, 15A in the twin-cell, each respective BLT terminal and BLC terminal voltage values are precharged to 0.5V and 0.3V for logic “0” state, respectively (or vise-versa for logic “1” state”). This results in developing a differential voltage (˜0.2V) between BLT and BLC proportional to the Vt shift (˜0.2V) in the cell; and 4) an erase state, e.g., when both BLT and BLC terminals 14 and 13 in the respective column are at 1.7 Volts with a wordline WL of −1.0 Volts applied to the gates of both transistors 15B and 15A.
Referring to FIG. 1A, generally, in electronic circuits having such bit memory array 10, the sense amplifier circuit 30 is provided for obtaining a stored bit value, i.e., perform a memory read operation. Typically, the sense amplifier 30 senses whether the T(true) or C(complement) transistor is programmed (Vt shifted). Such sense amplifier circuit 30 reads a selected memory cell BLT voltage and BLC voltage value at respective BLT terminal 14 and BLC terminal 16 conductors for cells selected by an applied WL voltage, and as selected by a respective corresponding column select transistor 22B and 22A to select the corresponding target cell via a corresponding Col_Select (T) select signal 23B and/or Col_Select (C) select signal 23A for complementary signals. The column select signals 23A and 23B are the same for one pair of BLT and BLC conductors. As shown in FIG. 1A, the conventional sense amplifier circuit 30 performs a differential read.
In the read operation, the programmed BLT (or BLC) value is dependent upon the sense circuitry of the sense amplifier and across process/voltage/temperature variations. However, the sense amplifier circuitry 30 needs to detect a differential voltage (e.g., typically ˜200 mV), e.g., shifts in Vt signal in the cell between the true/complement transistors 15A, 15B, that may result from a possible threshold voltage shift, e.g., during a read operation 35 of FIG. 1B. For example, the read state of about 0.5 volts (500 mV) for BLC (15A native state, or no Vt shift state) and the read state of about 0.3 volts (300 mV) for BLT (15B programmed state, or Vt shift state). This results in about a 0.2V (200 mV) data-dependent differential voltage built between BLT and BLC are shown in FIG. 1B for the sensing of BLT programmed state.
The use of twin-transistor, shown in FIG. 1A has been proposed for non-volatile memories to reduce sensitivity to device variation. However, if the twin transistor has initial VT offset prior to the programming, the twin cell approach causes a read failure unless the VT shift is more than the initial Vt offset. The initial Vt offset may be caused by the partial erasing condition after the programming for multiple write memory use.